As a conversion frequency of analog-to-digital converters (ADC) or digital-to-analog converters (DAC) increases, the challenge of evaluating the performance of such signal converters in production-scale quantities becomes progressively more difficult. One difficulty stems from conventional modes of testing signal converters, which, at higher frequencies, tend to reflect the combined performance of the device under test (DUT) and the test hardware, rather than the performance of the DUT alone.
When testing high speed and high performance ADCs and DACs in the GHz (Giga Hertz) frequency range, the limiting factor for performance on conventional ATE is determined more and more by jitter in the stimulus and conversion (sampling) clock signal. Jitter is the time variation of a periodic signal, often in relation to a reference clock source. Jitter may be observed in characteristics such as a frequency of successive pulses, or a phase of periodic signals. In respect to performance of ATE, however, a common assumption is that the limiting effect is caused by jitter in the conversion clock alone. Therefore, high costs and high development efforts are commonly expended in providing ultra-low jitter clocks, e.g. by developing low-jitter clock generators incorporating sophisticated phase-locked-loop (PLL) architectures.
ATE systems commonly use so-called arbitrary waveform generators (AWG) as an extremely flexible stimulus signal source for testing DUTs, such as, e.g., ADCs or DACs. Although other embodiments are conceivable, some AWGs synthesize waveforms using digital signal processing techniques, such as, e.g., so-called direct digital synthesis (DDS). Here, amplitude values of a period of an arbitrary 2m-periodic stimulus signal are stored as a so-called look-up table (LUT) in a computer memory, such as, e.g., a read-only memory (ROM). Advantageously, as many amplitude values as possible are stored at an as good as possible amplitude resolution. A direct digital synthesizer numerically calculates, in each clock cycle of a conversion clock signal, a digital phase φ of the periodic signal using a so-called phase accumulator, and determines associated digital amplitude values using the look-up table. Finally, an analog output signal is generated by a DAC from the digital amplitude values. A so-called tuning word forms the phase increment Δφ of the phase accumulator. That is, in a clock cycle n, phase φ[n] of the phase accumulator is increased by the phase increment Δφ, such as: φ[n]=φ[n−1]+Δφ. A digital phase word of the accumulator consists of a specific number of bits. Each time the phase accumulator overflows, a complete period of the periodic signal is generated. For this reason, phase increment Δφ of the phase accumulator, and the conversion clock frequency fCLK of the direct digital synthesizer define an output frequency fSTIM of the sinusoidal analog stimulus signal generated by the AWG or the DDS. The data used by an AWG for generating the analog stimulus signal for a DUT are typically ideally equidistant samples of a sine wave, wherein the conversion clock frequency fCLK may be lower than, equal to, or higher than the generated output or stimulus frequency fSTIM, depending on the phase increment. However, when the conversion clock contains jitter, the samples are output with offsets to the desired points in time. When the DUT, however, samples the AWG output signal (stimulus signal) using a stable sampling clock, the sampled DUT input signal appears to be phase modulated. In case the jitter is sinusoidal with a frequency of fJ, the sampled signal shows side lobes in its spectrum at frequencies fSTIM±m·fJ at amplitudes given by the Bessel functions of n-th order Jn(x), wherein x=π*Tjpp*fSTIM and Tjpp denotes a time between two subsequent peaks of a sinusoidal jitter.
FIG. 1 illustrates an exemplary spectrum for a generated sign wave test or stimulus signal with frequency fSTIM=100 MHz that contains 30 ps (pico seconds) sinusoidal peak-to-peak jitter (fJ=2 MHz). Since the phase modulation depth is small, the dominant spur is the first sidelobe at fSTIM±fJ that determines the signal-to-noise ratio (SNR). Its amplitude can be derived from the Bessel function of first order J1(x) which, for the case of small amplitudes x can be approximated by J1(x)≈x/2. Hence, the SNR may be expressed as:SNR[dB]=−20·log10(π/2·Tjpp·fSTIM),  (1)wherein Tjpp denotes a time between two subsequent peaks of the sinusoidal jitter. FIG. 2 illustrates the relationship expressed by Eq. (1) for a stable fSTIM=100 MHz ADC input signal versus the sinusoidal peak-to-peak jitter injected into the sampling clock of the ADC. Since the specified SNR for a state-of-the-art ADC (e.g. for a 200 Msps 16 bit ADC, Msps=Mega samples per second) is in the range of 70 dBc, a limit for the jitter between an input stimulus or test signal and a sampling clock is in the range of 2 ps peak-to-peak.
The generation of a low-jitter-clock with less than 2 ps peak-to-peak jitter in an ATE is challenging. However, it is even more challenging to distribute it to the many clock units in a large and complex system-on-chip (SoC) ATE and to the DUT keeping the jitter this low. Typically, when an ADC or DAC is to be tested in a test SoC device, the stimulus signal is generated in a mixed signal channel that derives its AWG conversion clock from a clock board that is synchronized with a PLL to a broadly distributed master clock. In contrast, a clock used as a conversion clock of the DUT ADC is generated from a digital channel using independent timing generators clocked from a different clock board that is also synchronized to the master clock with a PLL of its own.